Method of fabricating semiconductor device
US6545326B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 24, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.