Input delay correcting system and method for A/D converter and storage medium
US6545626B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input delay correcting system for an interleave type A/D converter is to be provided. Even if sampling clock signals fed to A/D converters 22 and 24 are not exactly shifted a half cycle from each other, a digital signal outputted from an output terminal 30d of an FIR filter 30 becomes a pulse of a tuning exactly shifted a half cycle from the sampling clock signal fed to the A/D converter 22. A digital signal outputted from, an output terminal 30c of the FIR filter 30 corresponds to a signal resulting from delaying an output of the A/D converter 22 by an integer multiple of the sampling clock signal cycle. Therefore, if the outputs from the output terminals 30c and 30d of the FIR filter 30 are made alternate by a multiplexer 40, the outputs of the A/D converters 22 and 24 can be exactly shifted a half cycle with respect to the sampling clock signals fed thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.