Multi-port memory cell with refresh port
US6545905B2 · kind B2 · utility
3Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage transistor is disclosed. The access transistors serve as access ports for the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.