Semiconductor memory device allowing spare memory cell to be tested efficiently
US6545921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first selector circuit selectively outputs eight of a plurality of data read from a regular memory cell array, to correspond to the number of data output for one read operation in a testing operation. A second selector circuit selectively outputs eight of a plurality of data read from a spare memory cell array. A third selector circuit in a test mode of operation receives an output of the first selector circuit and that of the second selector circuit and when the operation test of interest is to be conducted for a spare memory cell the third selector circuit outputs to a tester apparatus the output of the second selector circuit as testing output data TDout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.