High-speed radix 100 parallel adder
US6546411B1 · kind B1 · utility
8Cited by
8References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1999 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an improved method and apparatus for performing decimal arithmetic using conventional parallel binary adders. In a first aspect of the present invention, a method for implementing decimal arithmetic using a radix (base) 100 and a method for implementing radix 1000 numbering system are disclosed. The first aspect of the present invention implements decimal arithmetic utilizing radix 100, where one-hundred decimal numbers, 0 through 99, are represented using seven BCD bits. In a second aspect of the present invention, a specialized high-speed radix 100 parallel adder is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.