Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
US6546465B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor computer system comprising a plurality of processors, each comprising at least one memory cache and a memory. Each processor also includes a memory controller that includes a front-end section with a directory in-flight table and a decoder configured to read and write to each entry in the directory in-flight table. The front-end is configured to manage a directory based coherence protocol and validate directory information for each transaction in the directory in-flight table. Memory requests from the processors are allocated in the directory in-flight table and when multiple memory requests have the same memory address, redundant directory read and directory write requests are redirected and are executed internal to the memory controller. Each memory request entry in the directory in-flight table comprises the following fields: a memory address, a valid bit, a directory state, and an end bit. Transactions in the directory in-flight table with common memory address fields are linked in a list. A directory read request is executed for the first transaction in the list and a directory write request is executed for the last transaction in the list. When the valid bit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.