Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances
US6546541B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jun 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.