Higher voltage transistors for sub micron CMOS processes

US6548874B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Alec J. Morton · Plano, US
• Taylor R. Efland · Richardson, US
• Chin-Yu Tsai · Plano, US
• Jozef Mitros · Richardson, US
• Dan M. Mosher · Plano, US
• Sam Shichijo · Plano, US
• Keith E. Kunz · Bryan, US

Key dates

• Filing date: Sep 26, 2000
• Grant date: Apr 15, 2003
• Expiry date: Sep 26, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.