Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates
US6549040B1 · kind B1 · utility
21Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jul 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.