Circuit for providing clock signals with low skew

US6549045B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Bonnie I. Wang · Cupertino, US
• Chiakang Sung · Milpitas, US
• Khai Nguyen · San Jose, US
• Joseph Huang · معلمی نژاد, US
• Xiaobao Wang · Santa Clara, US
• In Whan Kim · San Jose, US
• Gopi Rangan · Santa Clara, US
• Yan Chong · San Jose, US
• Phillip Pan · Merced, US
• Tzung-Chin Chang · San Jose, US

Key dates

• Filing date: Jan 11, 2002
• Grant date: Apr 15, 2003
• Expiry date: Jan 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/135
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.