Inventor · San Jose, CA, US

Yan Chong

90Patents
16h-index
41Co-inventors
80Inventor score

Filing activity: May 22, 2001 → Aug 28, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6686769B1 Programmable I/O element circuit for high speed logic devices Human Necessities 100 Expired
US6433579B1 Programmable logic integrated circuit devices with differential signaling capabilities Electricity 89 Expired
US7590008B1 PVT compensated auto-calibration scheme for DDR3 Physics 42 Active
US6806733B1 Multiple data rate interface architecture Electricity 40 Expired
US7593273B2 Read-leveling implementations for DDR3 applications on an FPGA Electricity 40 Active
US7983094B1 PVT compensated auto-calibration scheme for DDR3 Physics 38 Active
US6911860B1 On/off reference voltage switch for multiple I/O standards Electricity 32 Expired
US9711189B1 On-die input reference voltage with self-calibrating duty cycle correction Physics 32 Active
US6766505B1 Parallel programming of programmable logic using register chains Electricity 25 Expired
US6870413B1 Schmitt trigger circuit with adjustable trip point voltages Electricity 23 Expired
US6630844B1 Supply voltage detection circuit Physics 22 Expired
US6825692B1 Input buffer for multiple differential I/O standards Electricity 21 Expired
US6661733B1 Dual-port SRAM in a programmable logic device Physics 19 Expired
US8565034B1 Variation compensation circuitry for memory interface Physics 19 Active
US7002384B1 Loop circuitry with low-pass noise filter Electricity 17 Expired
US6946872B1 Multiple data rate interface architecture Electricity 16 Expired
US7167023B1 Multiple data rate interface architecture Electricity 14 Expired
US7231536B1 Control circuit for self-compensating delay chain for multiple-data-rate interfaces Physics 12 Expired
US7215143B1 Input buffer for multiple differential I/O standards Electricity 12 Expired
US6549045B1 Circuit for providing clock signals with low skew Electricity 11 Expired
US7509223B2 Read-side calibration for data interface Electricity 11 Active
US7884619B1 Method and apparatus for minimizing skew between signals Electricity 11 Active
US7200769B1 Self-compensating delay chain for multiple-date-rate interfaces Physics 10 Expired
US8237475B1 Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop Electricity 10 Active
US7928770B1 I/O block for high performance memory interfaces Physics 10 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.