Dynamic logic MUX
US6549060B1 · kind B1 · utility
5Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/161
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.