Jonathan Lachman
14Patents
5h-index
13Co-inventors
63Inventor score
Filing activity: Dec 29, 1997 → Feb 7, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6271568A | Voltage controlled resistance modulation for single event upset immunity | Physics | 31 | Expired |
| US6275442A | Address decoder and method for ITS accelerated stress testing | Physics | 9 | Expired |
| US6314039A | Characterization of sense amplifiers | Physics | 7 | Expired |
| US6931607B2 | System and method for designing circuits in a SOI process | Physics | 6 | Expired |
| US6380779B1 | Edge-triggered, self-resetting pulse generator | Electricity | 5 | Expired |
| US6549060B1 | Dynamic logic MUX | Electricity | 5 | Expired |
| US6775812B2 | Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit | Electricity | 3 | Expired |
| US6944807B2 | Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays | Physics | 1 | Expired |
| US6940778B2 | System and method for reducing leakage in memory cells using wordline control | Physics | 1 | Expired |
| US6301140A | Content addressable memory cell with a bootstrap improved compare | Physics | 1 | Expired |
| US6836871B2 | Process and system for developing dynamic circuit guidelines | Physics | 1 | Expired |
| US10586583B2 | Ferroelectric random access memory sensing scheme | Physics | 0 | Active |
| US6580635B1 | Bitline splitter | Physics | 0 | Expired |
| US10978127B2 | Ferroelectric random access memory sensing scheme | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.