Method and system for improving the performance on SOI memory arrays in an SRAM architecture system
US6549450B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Follow…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.