Using multiple status bits per cell for handling power failures during write operations
US6549457B1 · kind B1 · utility
36Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cell memory may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.