Circuital structure for reading data in a non-volatile memory device
US6549473B2 · kind B2 · utility
6Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.