Memory device and method having reduced-power self-refresh mode
US6549479B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory device uses a gray code counter to generate addresses in a self-refresh operating mode so that only one bit of a row address generated by the counter changes state from one refresh cycle to the next. The row addresses are applied to a row address pre-decoder that coupled pre-decoded row address signals to a memory array in the memory device. The row address pre-decoder is operable to continuously couple at least some of the pre-decoded row address signals to the array from one refresh cycle to the next. As a result, only one a plurality of signal lines coupling the pre-decoded row address signals to the array must change state from one refresh cycle to the next, thereby minimizing the power consumed during the self-refresh mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.