Method and implementation of statistical detection of read after write and write after write hazards
US6550001B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for detecting instruction ordering dependencies. The apparatus includes a plurality of address comparators. Each comparator including a first input adapted to receive a first operand address from one of a plurality of instructions; a second input adapted to receive a second operand address from a second one of a plurality of instructions; and an output to transmit a logic signal responsive to a match between the first and second operand addresses. The address comparators receive the first operand address from a respective, different ones of the plurality of instructions; and a hardware structure to receive the match indications from the address comparators and to indicate a dependency responsive to the match indications from a first one and a second one of the address comparators. A method is provided for detecting instruction dependencies. The method includes receiving first and second pluralities of operand addresses that correspond to first and second pluralities of operands of instructions, and selecting ones of the first and second pluralities of operands. The ones of the first and second pluralities of operands have associated respective first and sec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.