Semiconductor chip input/output cell design and automated generation methods
US6550047B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated method for generating input/output (I/O) cells for an integrated circuit chip is provided. The method includes receiving a width parameter (as user requested data) for a desired I/O cell to be used for the integrated circuit chip. The method also includes receiving a tolerance parameter for the desired I/O cell. A cell library is selected to have a plurality of slices to meet the tolerance parameter. Then, the method proceeds to determine a number of the plurality of slices to be used to fit within the width parameter and to satisfy a drive strength parameter. The width parameter is then filled with a first row of the determined number of the plurality of slices. If the first row of slices (in either the N-channel device region or the P-channel device region) does not meet the drive strength parameter, additional rows (e.g., of dynamically adjusted height) can be added to provide an additional amount of transistor width that will meet the drive strength requirement. The generation of the I/O cells also includes the auto generation of P-tap regions, N-tap regions, isolation ring regions, and a receiver pre-driver region. The automated method is preferably provided as an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.