Method for generating optimized vector instructions from high level programming languages
US6550059B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1999 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Oct 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i.e., swapping positions of two operands.) Another embodiment comprises a software program (e.g., a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.