Method of manufacturing a semiconductor memory device
US6551866B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1999 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Apr 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.