Method for preventing borderless contact to well leakage
US6551901B1 · kind B1 · utility
11Cited by
11References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.