T-Ram array having a planar cell structure and method for fabricating the same
US6552398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.