Synchronous semiconductor device for adjusting phase offset in a delay locked loop
US6552587B2 · kind B2 · utility
32Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.