Current limiting technique for hybrid power MOSFET circuits
US6552889B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jul 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external resistance. When the voltage across the external resistance exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a non-conducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs will switch them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance load. If the voltage across the external resistance increases above the maximum, the PG mode of operation continues. PG mode of operation ceases and normal operation follows when the external resistance voltage remains below the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.