Column multiplexer for semiconductor memories
US6552952B2 · kind B2 · utility
59Cited by
9References
39Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 30, 2002 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical connection to the columns of the matrix, a selective connection device for selecting, in a first operation mode, at least one output line of the plurality of output lines in such a way as to connect it selectively to the input lines. In the first operation mode, the selective connection device selects a first group of output lines among the plurality of output lines, including at least three first lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.