Semiconductor memory device operable for both of CAS latencies of one and more than one
US6552959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Apr 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit, for the CAS latency of no less than two, stores read data in response to the second clock signal attaining the active state, and for the CAS latency of one, stores read data in response to the first clock signal and an equalization signal each attaining the active state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.