System and method for providing concurrent row and column commands
US6553449B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device. The communication paths further include a column command communication path that provides column commands to the memory devices, a column address communication path that provides column addresses for the column commands to the memory devices, a row command communication path that provides row commands to the memory devices, and a row address communication path that provides row addresses for the row commands to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.