Programmable element latch circuit
US6553556B1 · kind B1 · utility
21Cited by
6References
42Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.