Integrated circuit layout and verification method
US6553558B2 · kind B2 · utility
13Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.