Interconnect structure
US6555759B2 · kind B2 · utility
13Cited by
21References
55Claims
0Family size
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.