Buried channel strained silicon FET using a supply layer created through ion implantation
US6555839B2 · kind B2 · utility
147Cited by
49References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 16, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.