Trench gate fermi-threshold field effect transistors
US6555872B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jan 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth from the first surface. Spaced apart source and drain regions of the second conductivity type are included in the tub region of second conductivity type at the surface, to define single conductivity junctions of the second conductivity type with the tub region of second conductivity type. The spaced apart source and drain regions extend into the tub region a second depth that is less than the first depth. A trench is included in the tub region, between the spaced apart source and drain regions, and extending from the surface into the tub region to a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is included in the trench. Source and drain electrodes are provided on the surface that electrically contact the source and drain regions respectively. These field effect transistors may be fabricated by forming a tub region of second conductivity type in a semiconductor substrate …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.