Semiconductor package having stacked semiconductor chips and method of making the same
US6555917B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Oct 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be a ball grid array substrate or a metal leadframe. The stack of semiconductor chips is mounted to the substrate. Each semiconductor chip has a plurality of bond pads on an active surface thereof. The bond pads of the first semiconductor chip face corresponding ones of the bond pads of the second semiconductor chip, and are joined thereto through an electrically conductive joint. One of a plurality of bond wires extend from each of the joints to the substrate. Accordingly, pairs of bond pads of the first and second semiconductor chips are electrically interconnected, and are electrically connected to the substrate through the respective bond wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.