Stacked semiconductor device including improved lead frame arrangement
US6555918B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Mar 25, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.