Integrated circuit including ESD circuits for a multi-chip module and a method therefor
US6556409B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.