High-speed cycle clock-synchrounous memory device
US6556507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2002 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S·N·F.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.