Rounding anticipator for floating point operations
US6557021B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Mar 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.