High speed peripheral interconnect apparatus, method and system
US6557068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.