Cache chain structure to implement high bandwidth low latency cache memory subsystem
US6557078B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.