Scaling logic for event based test system
US6557133B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An event based test system having a scaling function for freely changing the timings of events for generating test signals for testing an electronics device under test (DUT) in proportion to a scale factor. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory, a summing and scaling logic for summing the timing data and modifying the timing data based on the scale factor to produce an overall time of each event relative to a predetermined reference point, and an event generator for generating each event based on the overall time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.