Method for preserving regularity during logic synthesis
US6557159B1 · kind B1 · utility
11Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | May 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a method for maintaining regularity in a netlist during logic synthesis. The method determines a global regularity for the netlist. The method determines a group of elements in the netlist having similar regularity signatures. Further, the method applies a transform to the group of elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.