Chip-over-chip integrated circuit package
US6558978B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Nov 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages. Packages in accordance with the invention have increased access speeds between chips and reduced total chip package footprint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.