Non-volatile memory cells with selectively formed floating gate

US6559008B2 · kind B2 · utility

Assignee

• Hynix Semiconductor America, Inc. · US

Inventors

• Peter Rabkin · Cupertino, US
• Hsingya Arthur Wang · Saratoga, US
• Kai-Cheng Chou · San Jose, US

Key dates

• Filing date: Oct 4, 2001
• Grant date: May 6, 2003
• Expiry date: Oct 4, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.