Inventor · Cupertino, CA, US

Peter Rabkin

133Patents

20h-index

73Co-inventors

93Inventor score

Filing activity: Feb 2, 2001 → Jul 13, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9530790B1	Three-dimensional memory device containing CMOS devices over memory stack structures	Electricity	108	Active
US8847302B2	Vertical NAND device with low capacitance and silicided word lines	Electricity	94	Active
US9881929B1	Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof	Electricity	73	Active
US9230985B1	Vertical TFT with tunnel barrier	Electricity	73	Active
US9177966B1	Three dimensional NAND devices with air gap or low-k core	Electricity	58	Active
US9230980B2	Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device	Electricity	46	Active
US9478495B1	Three dimensional memory device containing aluminum source contact via structure and method of making thereof	Electricity	42	Active
US9634097B2	3D NAND with oxide semiconductor channel	Electricity	39	Active
US8933502B2	3D non-volatile memory with metal silicide interconnect	Electricity	38	Active
US8951859B2	Method for fabricating passive devices for 3D non-volatile memory	Electricity	36	Active
US9515085B2	Vertical memory device with bit line air gap	Electricity	35	Active
US9425299B1	Three-dimensional memory device having a heterostructure quantum well channel	Electricity	35	Active
US8643142B2	Passive devices for 3D non-volatile memory	Electricity	32	Active
US9721963B1	Three-dimensional memory device having a transition metal dichalcogenide channel	Electricity	31	Active
US9711229B1	3D NAND with partial block erase	Electricity	31	Active
US6559008B2	Non-volatile memory cells with selectively formed floating gate	Electricity	30	Expired
US6818504B2	Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications	Electricity	25	Expired
US10115459B1	Multiple liner interconnects for three dimensional memory devices and method of making thereof	Physics	23	Active
US11107516B1	Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same	Electricity	20	Active
US9530506B2	NAND boosting using dynamic ramping of word line voltages	Physics	20	Active
US9449985B1	Memory cell with high-k charge trapping layer	Electricity	19	Active
US9331093B2	Three dimensional NAND device with silicon germanium heterostructure channel	Electricity	18	Active
US9449980B2	Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure	Electricity	18	Active
US10319680B1	Metal contact via structure surrounded by an air gap and method of making thereof	Electricity	17	Active
US9287290B1	3D memory having crystalline silicon NAND string channel	Electricity	16	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.