Method for avoiding notching in a semiconductor interconnect during a metal etching step
US6559062B1 · kind B1 · utility
2Cited by
18References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Dec 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.