Test pattern for evaluating a process of silicide film formation
US6559475B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Feb 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation. The test pattern in accordance with the present invention includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The second pattern includes: a pair of polycide patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region; and an active silicide strip formed between the first polycide strip and the second polycide strip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.