Patterning of content areas in multilayer metalization configurations of semiconductor components

US6559547B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Matthias Lehr · Dresden, DE
• Albrecht Kieslich · Radebeul, DE
• Peter Thieme · Dresden, DE
• Lars Voland · Dresden, DE

Key dates

• Filing date: Sep 15, 2000
• Grant date: May 6, 2003
• Expiry date: Sep 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31053
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.