Spread spectrum type clock generating circuit
US6559698B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.