Chip package with molded underfill
US6560122B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.